The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to circuits and methods for a static random access memory using vertical transistors.
Modem electronic systems typically include a data storage device such as a dynamic random access memory (DRAM), static random access memory (SRAM) or other conventional memory device. The memory device stores data in vast arrays of memory cells. Each cell conventionally stores a single bit of data (a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0xe2x80x9d) and can be individually accessed or addressed.
Electronic systems, e.g., computers, conventionally store data during operation in the memory device. As these systems become more sophisticated, they require more and more memory in order to keep pace with the increasing complexity of software based applications that run on the systems. Thus, as the technology relating to memory devices has evolved, designers have tried to increase the density of memory cells in the memory device. The electronics industry strives to decrease the size of the memory cells. This allows a larger number of memory cells to be fabricated without substantially increasing the size of the semiconductor wafer.
Static random access memory or xe2x80x9cSRAMxe2x80x9d is one type of memory device that is used with computers. Conventionally, an SRAM device includes an array of addressable memory cells. Each cell includes a four transistor flip-flop and access transistors that are coupled to input/output nodes of the flip-flop. Data is written to the memory cell by applying a high or low logic level to one of the input/output nodes of the flip-flop through one of the access transistors. When the logic level is removed from the access transistor, the flip-flop retains this logic level at the input/output node. Data is read out from the flip-flop by turning on the access transistor.
Memory devices are fabricated using photolithographic techniques that allow semiconductor and other materials to be manipulated to form integrated circuits as is known in the art. These photolithographic techniques essentially use light that is focussed through lenses to define patterns in the materials with microscopic dimensions. The equipment and techniques that are used to implement this photolithography provide a limit for the size of the circuits that can be formed with the materials. Essentially, at some point, the lithography cannot create a fine enough image with sufficient clarity to decrease the size of the elements of circuit. In other words, there is a minimum dimension that can be achieved through conventional photolithography. This minimum dimension is referred to as the xe2x80x9ccritical dimensionxe2x80x9d (CD) or minimum feature size (F) of the photolithographic process.
The minimum feature size imposes one constraint on the size of conventional SRAM memory cells. Conventionally, SRAM cells have used a surface area on a substrate that is approximately equal to 120 feature squares. Recently, researchers have designed an SRAM cell in an area of approximately 100 feature squares. In order to keep up with the demands for higher capacity memory devices, designers need to further reduce the size of the memory cells.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an SRAM cell which uses less surface area than conventional SRAM cells.
The above mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A circuit and method for a static random access memory cell are described which use vertical transistors with a surface area of approximately 32 feature squares (xe2x80x9cF2xe2x80x9d) to implement a six transistor cell.
In particular, an illustrative embodiment of the present invention includes a memory cell. The memory cells has a flip-flop that includes a cross-coupled pair of inverters. The inverters each include a pair of complementary, vertical transistors. A gate contact interconnects the gates of the inverters and acts as the input of the inverter. A shunt interconnects a first source/drain region of the complementary transistors and acts as the output of the inverter. A first vertical, access transistor is also included. The first vertical, access transistor has a gate that is coupled to a word line, a first source/drain region that is coupled to the output of one of the inverters, and a second source/drain region that is coupled to a first bit line. A second vertical, access transistor is also provided. The second vertical, access transistor has a gate that is coupled to the word line, a first source/drain region that is coupled to the output of the other inverter, and a second source/drain region that is coupled to a second bit line.
In another embodiment, a method for forming a memory cell is provided. The method includes forming vertical bars of semiconductor material on a surface of a semiconductor wafer. The bars have vertically aligned first source/drain, body and second source/drain regions. Individual pillars of semiconductor material are separated out from the vertical bars to form vertical transistors. Vertical transistors from adjacent bars with body regions of different conductivity types are coupled to form inverters. The inverters are cross-coupled to form an array of flip-flops. Vertical access transistors are coupled to inputs/outputs of the flip-flops.
In another embodiment, an electronic system is provided. The electronic system includes a microprocessor. The microprocessor is coupled to a static random access memory. The memory has an array of six-transistor memory cells. Each memory cell is formed with six vertical transistors on a surface area of approximately 32 feature (F) squares.
In another embodiment, a memory device is provided. The memory device includes a number of word lines and a number bit lines that are disposed to form an array. A number of memory cells are addressably disposed at intersections of word and bit lines. Each memory cell includes a cross-coupled pair of inverters that are formed from vertical transistors. Each memory cell also includes a pair of vertical, access transistors that are each coupled to the output of one of the inverters. Each vertical, access transistor in a memory cell is coupled to a selected word line and a selected bit line. A word line decoder is coupled to the word lines of the memory array and selectively activates the word lines of the array. A sense amplifier is coupled to the bit lines of the array of memory cells. A bit line decoder is coupled to the sense amplifier and selects bit lines for reading and writing data to and from the memory cells.